This talk will cover the fabrication and operation of silicon chips, from the industry leading fabrication facilities to the detailed operation of an integrated system on chip (SoC). The starting point will be the humble p-n junction familiar from A-level physics, or an undergraduate physics course syllabus.
The tour will continue to build-up to the physics of the field effect transistor (FET), which is the building block of the silicon revolution. From this point, the foundations are laid for implementation of the familiar logical family of functions which allow the myriad of applications we see today, where literally millions of FETs are used to design the very large scale integrated (VLSI) circuits which are the main subject of this talk.
A “bottom-up” approach to the underlying technology will be employed so as to convey something of the fantastically complicated processing steps required to achieve current levels of integration in a so-called silicon foundry. The levels of cleanroom cleanliness and vast cost of these facilities will be laid bare, along with a few clues to the future direction of travel and “ones to watch”!
Lectures start at 19:30 with tea/coffee from 19:00